Spatio-temporal Learning with Arrays of Analog Nanosynapses

Emerging nanodevices such as resistive memories are being considered for hardware realizations of a variety of artificial neural networks (ANNs), including highly promising online variants of the learning approaches known as reservoir computing (RC) and the extreme learning machine (ELM). We propose an RC/ELM inspired learning system built with nanosynapses that performs both on-chip projection and regression operations. To address time-dynamic tasks, the hidden neurons of our system perform spatio-temporal integration and can be further enhanced with variable sampling or multiple activation windows. We detail the system and show its use in conjunction with a highly analog nanosynapse device on a standard task with intrinsic timing dynamics- the TI-46 battery of spoken digits. The system achieves nearly perfect (99%) accuracy at sufficient hidden layer size, which compares favorably with software results. In addition, the model is extended to a larger dataset, the MNIST database of handwritten digits. By translating the database into the time domain and using variable integration windows, up to 95% classification accuracy is achieved. In addition to an intrinsically low-power programming style, the proposed architecture learns very quickly and can easily be converted into a spiking system with negligible loss in performance- all features that confer significant energy efficiency.Comment: 6 pages, 3 figures. Presented at 2017 IEEE/ACM Symposium on Nanoscale architectures (NANOARCH

DSP-like analogue processing unit for smart image sensors”, in Int

SUMMARY An electronic retina featuring DSP-like programmable analogue processing is addressed. The motivations for designing such an original smart image sensor are accounted for. The architecture of the circuit is described and then the two more important building blocks are detailed. Finally, the practical implementation and tests results are given so as to validate the approach. MOTIVATIONS To face the challenge of the image processing at video rate, numerous solutions were developed. The electronic retinas appear among one of the most prosperous axes of research First of all, for a given silicon area, ÿnding a satisfactory compromise between the resolution and the completeness of the implemented analogue functions is a di cult task. This dilemma can either lead in two impasses. On the one hand, the retinas may o er a rich set of operators but at the expense of the resolution and the ÿll factor. Conversely, the circuit may feature an operative pan too much unadorned to a ord exploitable results

Cross-point architecture for spin transfer torque magnetic random access memory

Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using a STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture

Vers une nouvelle génération de rétines programmables

Dans ce papier, nous présentons la définition d'une architecture de capteur d'images intégrant un traitement parallèle mixte analogique-numérique. L'architecture originale d'une unité de calcul analogiques programmable est notamment décrite

Embracing the Unreliability of Memory Devices for Neuromorphic Computing

The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near- or in-memory. However, this type of computation is not compatible with conventional ECC, and has to deal with device unreliability. Inspired by the architecture of animal brains, we present a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC. We also show that using low-energy but error-prone programming conditions only slightly reduces network accuracy

A gate-variable spin current demultiplexer based on graphene

Spintronics, which utilizes spin as information carrier, is a promising solution for nonvolatile memory and low-power computing in the post-Moore era. An important challenge is to realize long distance spin transport, together with efficient manipulation of spin current for novel logic-processing applications. Here, we describe a gate-variable spin current demultiplexer (GSDM) based on graphene, serving as a fundamental building block of reconfigurable spin current logic circuits. The concept relies on electrical gating of carrier density dependent conductivity and spin diffusion length in graphene. As a demo, GSDM is realized for both single-layer and bilayer graphene. The distribution and propagation of spin current in the two branches of GSDM depend on spin relaxation characteristics of graphene. Compared with Elliot-Yafet spin relaxation mechanism, D'yakonov-Perel mechanism results in more appreciable gate-tuning performance. These unique features of GSDM would give rise to abundant spin logic applications, such as on-chip spin current modulators and reconfigurable spin logic circuits.Comment: 18 pages,3 figures,1 tabl

Physical Realization of a Supervised Learning System Built with Organic Memristive Synapses

International audienceMultiple modern applications of electronics call for inexpensive chips that can perform complex operations on natural data with limited energy. A vision for accomplishing this is implementing hardware neural networks, which fuse computation and memory, with low cost organic electronics. A challenge, however, is the implementation of synapses (analog memories) composed of such materials. In this work, we introduce robust, fastly programmable, nonvolatile organic memristive nanodevices based on electrografted redox complexes that implement synapses thanks to a wide range of accessible intermediate conductivity states. We demonstrate experimentally an elementary neural network, capable of learning functions, which combines four pairs of organic memristors as synapses and conventional electronics as neurons. Our architecture is highly resilient to issues caused by imperfect devices. It tolerates inter-device variability and an adaptable learning rule offers immunity against asymmetries in device switching. Highly compliant with conventional fabrication processes, the system can be extended to larger computing systems capable of complex cognitive tasks, as demonstrated in complementary simulations

On the alleged simplicity of impure proof

Roughly, a proof of a theorem, is “pure” if it draws only on what is “close” or “intrinsic” to that theorem. Mathematicians employ a variety of terms to identify pure proofs, saying that a pure proof is one that avoids what is “extrinsic,” “extraneous,” “distant,” “remote,” “alien,” or “foreign” to the problem or theorem under investigation. In the background of these attributions is the view that there is a distance measure (or a variety of such measures) between mathematical statements and proofs. Mathematicians have paid little attention to specifying such distance measures precisely because in practice certain methods of proof have seemed self- evidently impure by design: think for instance of analytic geometry and analytic number theory. By contrast, mathematicians have paid considerable attention to whether such impurities are a good thing or to be avoided, and some have claimed that they are valuable because generally impure proofs are simpler than pure proofs. This article is an investigation of this claim, formulated more precisely by proof- theoretic means. After assembling evidence from proof theory that may be thought to support this claim, we will argue that on the contrary this evidence does not support the claim